Distributed Clock (Synchronization)
***EtherCAT is an open, high-performance Ethernet-based fieldbus system. The development goal of EtherCAT was to apply Ethernet to automation applications which require short data update times (also called cycle times) with low communication jitter (for synchronization purposes) and low hardware costs feature that allows synchronization, with a reference clock, of all EtherCAT slaves and the master. This solves problems related to clock-shifting between the master and the devices.
This mechanism also leads to very low jitter of significantly less than 1 µs. Even if the communication cycle jitters, it is still compliant with the IEEE 1588 Precision Time Protocol standard.
Therefore, EtherCAT does not require special hardware in the master device and can be implemented in software on any standard EthernetEthernet is a large, diverse family of frame-based computer networking technologies that operate at many speeds for local area networks (LANs) MAC, even without a dedicated communication coprocessor.
The typical process of establishing a distributed clock is initiated by the master by sending a broadcast to all slaves at a specific address. On reception of this message, all slaves latch the value of their internal clock twice, once when the message is received and once when it returns (remember EtherCAT has a ring topology). The master can then read all latched values and calculate the delay for each slave. This process can be repeated as many times as required to reduce jitter and to average out values. Total delays are calculated for each slave depending on their position in the slave-ring and are uploaded to an offset register. Finally the master issues a broadcast read-write on the system clock, which makes the first slave the reference clock and forcing all other slaves to set their internal clock appropriately with the now known offset.
To keep the clocks synchronized after initialization, the master or slave must regularly send out the broadcast again to counter any effects of speed difference between the internal clocks of each slave. Each slave has to adjust the speed of their internal clock or implement an internal correction mechanism whenever they have to adjust.
The system clock is specified as a 32-bit counter with a base unit of 1 ns starting at January 1st 2000, 0:00.
Figure 5-53: Synchronicity and Simultaneousness
Scope view of two distributed devices with 300 nodes and 120 m of cable between them.
